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FAN6754A -- Highly Integrated Green-Mode PWM Controller
September 2010
FAN6754A Highly Integrated Green- Mode PWM Controller
Brownout and VLimit Adjustment by HV Pin Features
High-Voltage Startup AC Input Brownout Protection with Hysteresis Monitor HV to Adjust VLimit Low Operating Current: 1.5mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 13V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Open-Loop Protection (OLP); Restart for MR, Latch for ML SENSE Short-Circuit Protection (SSCP) Built-in 8ms Soft-Start Function
Description
The highly integrated FAN6754A PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency under light-load conditions. Under zero-load and very light-load conditions, FAN6754A saves PWM pulses by entering deep burst mode. This burst mode function enables the power supply to meet international power conservation requirements. FAN6754A integrates a frequency-hopping function internally to reduce EMI emission of a power supply with minimum line filters. Built-in synchronized slope compensation is accomplished by proprietary HV monitor to adjust VLimit for constant output power limit over universal AC input range. The gate output is clamped at 13V to protect the external MOSFET from over-voltage damage. Other protection functions include AC input brownout protection with hysteresis, SENSE pin short-circuit protection, and VDD over-voltage protection. For overtemperature protection, an external NTC thermistor can be applied to sense the external switcher's temperature. When VDD OVP or OTP are activated, an internal latch circuit is used to latch-off the controller. The latch mode is reset when the VDD supply is removed. FAN6754A is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters
Ordering Information
Part Number
FAN6754AMRMY FAN6754AMLMY
Operating Temperature Range
-40 to +105C
Package
8-Pin, Small Outline Package (SOP)
Packing Method
Tape & Reel
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
www.fairchildsemi.com
FAN6754A -- Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1 www.fairchildsemi.com 2
FAN6754A -- Highly Integrated Green-Mode PWM Controller
Marking Information
F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (M=SOP) P - Y: Package (Green) M - Manufacture Flow Code
ZXYTT 6754MR ATPM
ZXYTT 6754ML ATPM
Figure 3. Top Mark
Pin Configuration
SOP-8 GND FB NC HV 1 2 3 4 8 7 6 5 GATE VDD SENSE RT
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
1
Name
GND
Description
Ground. This pin is used for the ground potential of all the pins. A 0.1F decoupling capacitor placed between VDD and GND is recommended. Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined by this pin and the current-sense signal from Pin 6. FAN6754A performs open-loop protection (OLP); if the FB voltage is higher than a threshold voltage (around 4.6V) for more than 56ms, the controller latches off the PWM. No Connection High-Voltage Startup. This pin is connected to the line input via a 1N4007 and 200k resistor to achieve brownout and high/low line compensation. Once the voltage on the HV pin is lower than the brownout voltage, PWM output turns off. High/low line compensation dominates the cycle-by-cycle current limiting to achieve constant output power limiting with universal input. Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND. The impedance of the NTC decreases at high temperatures. Once the voltage on the RT pin drops below the threshold voltage, the controller latches off the PWM. If RT pin is not connected to NTC resistor for Over-Temperature Protection, a 100K series one resistor is recommended to ground to prevent from noise interference. This pin is limited by an internal clamping circuit. Current Sense. This pin is used to sense the MOSFET current for the current-mode PWM and current limiting. Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external bulk capacitor of typically 47F. The threshold voltages for turn-on and turn-off are 17V and 10V, respectively. The operating current is lower than 2mA. Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped below 13V.
2 3 4
FB NC HV
5
RT
6 7 8
SENSE VDD GATE
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD VFB VSENSE VRT VHV PD JA TJ TSTG TL ESD DC Supply Voltage
(1,2)
Parameter
FB Pin Input Voltage SENSE Pin Input Voltage RT Pin Input Voltage HV Pin Input Voltage Power Dissipation (TA50C) Thermal Resistance (Junction-to-Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model; Electrostatic Discharge Capability, JESD22-A114 All Pins Except HV Pin Charged Device Model; JESD22-C101
Min.
-0.3 -0.3 -0.3
Max.
30 7.0 7.0 7.0 500 400 150
Unit
V V V V V mW C/W C C C V
-40 -55
+125 +150 +260 4500 1500
Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD with HV pin: CDM=1000V and HBM=500V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA RHV
Parameter
Operating Ambient Temperature HV Startup Resistor
Min.
-40 150
Typ.
200
Max.
+105 250
Unit
C k
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25C unless otherwise noted.
Symbol
VDD Section VOP VDD-ON VDD-OFF VDD-OLP VDD-LH VDD-AC IDD-ST IDD-OP1 IDD-OP2 ILH IDD-OLP VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage IDD-OLP Off Voltage Threshold Voltage on VDD Pin for Latch-Off Release Voltage Threshold Voltage on VDD Pin for Disable AC Recovery to Avoid Startup Failed Startup Current Operating Supply Current, PWM Operation Operating Supply Current, Gate Stop Operating Current at PWM-Off Phase Under Latch-Off Conduction
Conditions
Min.
Typ.
Max.
24
Units
V V V V V V A mA mA A A V s
16 9 5.5 3.5 VDD-OFF +2.8 VDD-ON - 0.16V VDD=20V, FB=3V Gate Open VDD=20V, FB=3V VDD=5V 30 170 24 75
17 10 6.5 4.0 VDD-OFF +3.3
18 11 7.5 4.5 VDD-OFF +3.8 30
1.5 1.0 60 200 25 165
2.0 1.5 90 230 26 255
Internal Sink Current Under LatchVDD-OLP+0.1V Off Conduction VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time
HV Section IHV IHV-LC Supply Current from HV Pin Leakage Current after Startup VAC=90V(VDC=120V), VDD=0V HV=700V, VDD=VDDOFF+1V DC Source Series R=200k to HV Pin See Equation 1 DC Source Series R=200k to HV Pin See Equation 2 DC Source Series R=200k to HV Pin FB > VFB-N FB < VFB-G FB > VFB-N FB < VFB-G 65 180 92 2.0 3.5 1 5.0 20 mA A
VAC-OFF
Brownout Threshold
102
112
V
VAC-ON VAC tS-CYCLE tH-TIME tD-AC-OFF
Brownin Threshold VAC-ON - VAC-OFF Line Voltage Sample Cycle Line Voltage Hold Period PWM Turn-off Debounce Time
104 6
114 12 220 650 20 75 235
124 18
V V s s
85 290
ms ms
Continued on page 7...
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
Figure 5. Brownout Circuit
VIN-ON VIN-OFF VIN
Gate
Gate start Brownout debounce time Gate stop
Figure 6. Brownout Behavior
Figure 7. VDD-AC and AC Recovery
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise noted.
Symbol
Oscillator Section fOSC tHOP fOSC-G fDV fDT
Parameter
Conditions
Center Frequency Hopping Range FB > VFB-N FB=VFB-G VDD=11V to 22V TA=-40 to +105C
Min.
61 3.7 3.9 10.2 19
Typ.
65 4.2 4.4 11.5 22
Max. Units
69 4.7 4.9 12.8 25 5 5
Frequency in Normal Mode Hopping Period Green-Mode Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation Input Voltage to Current-Sense Attenuation Input Impedance Output High Voltage FB Open-Loop Trigger Level Delay Time of FB Pin Open-Loop Protection Green-Mode Entry FB Voltage
KHz ms ms KHz % %
Feedback Input Section AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N 1/4.5 14 FB Pin Open 4.8 4.3 50 Pin, FB Voltage (FB =VFB-N) Hopping Range VFB-G VFB-ZDCR VFB-ZDC Green-Mode Ending FB Voltage FB Threshold Voltage for Zero-Duty Recovery FB Threshold Voltage for Zero-Duty Pin, FB Voltage (FB =VFB-G) Hopping Range 2.6 3.7 2.1 1.27 1.9 1.8 1/4.0 16 5.0 4.6 56 2.8 4.2 2.3 1.45 2.1 2.0 1/3.5 18 5.2 4.9 62 3.0 4.7 2.5 1.62 2.3 2.2 V/V k V V ms V kHz V kHz V V
Continued on the following page...
PWM Frequency
fOSC
fOSC-G
VFB-ZDC VFB-ZDCR VFB-G
VFB-N
VFB
Figure 8. VFB vs. PWM Frequency
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise noted.
Symbol
Current-Sense Section tPD tLEB VLimit-L VLimit-H VSSCP tON-SSCP tD-SSCP tSS DCYMAX VGATE-L VGATE-H IGATESOURCE
Parameter
Delay to Output Leading-Edge Blanking Time Current Limit at Low Line (VAC=86V) Current Limit at High Line (VAC=259V) On Time for VSSCP Checking
Conditions
Min.
Typ.
100
Max. Units
250 330 0.49 0.42 0.07 4.8 180 9 92 1.5 ns ns V V V s s ms % V V mA mA
230 VDC=122V, Series R=200k to HV VDC=366V, Series R=200k to HV 0.43 0.36 0.03 4.0 60 7 86 VDD=15V, IO=50mA VDD=12V, IO=50mA VDD=15V 8 300 250 Startup Time
280 0.46 0.39 0.05 4.4 120 8 89
Threshold Voltage for SENSE Short-Circuit Protection Delay for SENSE Short-Circuit Protection VSENSE<0.05V Soft-Start Time Maximum Duty Cycle Gate Low Voltage Gate High Voltage
(4) (4)
GATE Section
IGATE-SINK Gate Sink Current
Gate Source Current Gate Rising Time Gate Falling Time
VDD=15V, GATE=6V VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=22V
tr tf VGATECLAMP
100 50 9 13 17
ns ns V
Gate Output Clamping Voltage
RT Section IRT VRTTH1 VRTTH2 Output Current from RT Pin Over-Temperature Protection Threshold Voltage 0.7V VRT 1.05V, after 12ms Latch Off VRT 0.7V, After 100s Latch Off VRTTH2 VRT VRTTH1 FB > VFB-N Over-Temperature Latch-Off Debounce tD-OTP2 Note: 4. Guaranteed by design. VRTTH2 VRT VRTTH1 FB < VFB-G VRT< VRTTH2, FB > VFB-N VRT< VRTTH2, FB < VFB-G 92 1.000 0.65 14 40 110 320 100 1.035 0.70 16 51 185 605 108 1.070 V 0.75 18 ms 62 260 890 s A
tD-OTP1
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics (Continued)
Figure 9. Startup Current (IDD-ST) vs. Temperature
Figure 10.
Operation Supply Current (IDD-OP1) vs. Temperature
Figure 11. Start Threshold Voltage (VDD-ON) vs. Temperature
Figure 12. Minimum Operating Voltage (VDD-OFF) vs. Temperature
Figure 13.
Supply Current Drawn from HV Pin (IHV) vs. Temperature
Figure 14.
HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature
Figure 15. Frequency in Normal Mode (fOSC) vs. Temperature
Figure 16.
Maximum Duty Cycle (DCYMAX) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics (Continued)
Figure 17. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature
Figure 18. Delay Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature
Figure 19. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature
Figure 20. Output Current from RT Pin (IRT) vs. Temperature
Figure 21. Over-Temperature Protection Threshold Voltage (VRTTH1) vs. Temperature
Figure 22. Over-Temperature Protection Threshold Voltage (VRTTH2) vs. Temperature
Figure 23. Brownin (VAC-ON) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
Figure 24. Brownout (VAC-OFF) vs. Temperature
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
For startup, the HV pin is connected to the line input through an external diode and resistor; RHV, (1N4007 / 200K recommended). Peak startup current drawn from the HV pin is (VACx 2 ) / RHV and charges the hold-up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6754A to keep the VDD until the auxiliary winding of the main transformer provides the operating current.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.
Operating Current
Operating current is around 1.5mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance.
Slope Compensation
The sensed voltage across the current-sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6754A inserts a synchronized, positive-going, ramp at every switching cycle.
Green-Mode Operation
The proprietary green-mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage (VFB-N), the switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz.
Constant Output Power Limit
When the SENSE voltage across sense resistor RSENSE reaches the threshold voltage, around 0.46V for low-line condition, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD * VIN / LP. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by the HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the current limiting comparator. This results in a lower current limit at highline inputs than at low-line inputs.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB-0.6)/4, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.46V for low-line output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.
Brownout and Constant Power Limited by the HV Pin
Unlike previous PWM controllers, FAN6754A's HV pin can detect the AC line voltage brownout function and adjust the current limit. Using a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and is stored in a register at each sampling cycle. When internal update time is met, this peak value is used for brownout and current-limit level judgment. Equation 1 and 2 calculate the level of brownin or brownout converted to RMS value. For power saving, FAN6754A enlarges the sampling cycle to lower the power loss from HV sampling at light-load condition.
VAC - ON (RMS) = ( 0.9V x
VAC - OFF (RMS)= ( 0.81V x
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 17V and 10V, respectively. During startup, the holdup capacitor must be charged to 17V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD until the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10V during startup. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup.
(RHV +1.6) )/ 2 1.6
(RHV +1.6) )/ 2 1.6
(1) (2)
where RHV is in k.
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1 www.fairchildsemi.com 11
FAN6754A -- Highly Integrated Green-Mode PWM Controller
The HV pin can perform current limit to shrink the tolerance of Over-Current Protection (OCP) under full range of AC voltage, to linearly current limit curve, as shown in Figure 25. FAN6754A also shrinks the Vlimit 2 level by half to lower the I RSENSE loss to increase the heavy-load efficiency.
0.47 0.46 0.45 0.44 Vlimit (V) 0.43 0.42 0.41 0.4 0.39 0.38 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 DC Voltage on HV Pin (V)
Thermal Protection
An NTC thermistor, RNTC, in series with resistor RA, can be connected from the RT pin to ground. A constant current, IRT, is output from the RT pin. The voltage on the RT pin can be expressed as VRT=IRT * (RNTC + RPTC), where IRT is 100A. At high ambient temperature, RNTC is smaller, such that VRT decreases. When VRT is less than 1.035V (VRTTH1), the PWM turns off after 16ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2), the PWM turns off after 185s (tD-OTP2). If the RT pin is not connected to NTC resistor for over-temperature protection, connecting a series one 100K resistor to ground to prevent from noise interference is recommended. This pin is limited by an internal clamping circuit.
Limited Power Control
The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. When VDD goes below the turn-off threshold (10V) the controller is totally shut down and VDD is continuously discharged to VDD-OLP (6.5V) by IDD-OLP to lower the average input power. This is called two-level UVLO. VDD is cycled again. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions.
Figure 25. Linearly Current Limit Curve
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage due to abnormal conditions. If the VDD voltage is over the overvoltage protection voltage (VDD-OVP) and lasts for tDVDDOVP, the PWM pulses are disabled until VDD drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops.
Sense-Pin Short-Circuit Protection
The FAN6754A provides safety protection for Limited Power Source (LPS) tests. When the sense resistor is shorted by soldering during production, the pulse-bypulse current limiting loses efficiency for the purpose of providing over-power protection for the unit. The unit may be damaged when the loading is larger than the maximum load. To protect against a short circuit across the current-sense resistor, the controller is designed to immediately shut down if a continuously low voltage (around 0.05V/120s) on the SENSE pin is detected.
Noise Immunity
Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6754A, and increasing the power MOS gate resistance improve performance.
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A -- Highly Integrated Green-Mode PWM Controller
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 26. 8-Pin Small Outline Package (SOP) Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
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FAN6754A-- Highly Integrated Green-Mode PWM Controller
(c) 2010 Fairchild Semiconductor Corporation FAN6754A * Rev. 1.0.1
www.fairchildsemi.com 14

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